Press Releases
CriticalBlue's Cascade Validated with the Synopsys RTL Implementation Flow
Cascade Accurately Predicts Downstream Performance and Gate Count
San Jose, California - January 21, 2005 - CriticalBlue, a start-up company focused on delivering tools for accelerating software in embedded microprocessor applications, has completed a benchmark project validating its Cascade tool with respect to Synopsys®' RTL implementation flow. Working with a leading semiconductor company who defined the embedded software benchmark example and its target gate count and performance constraints, Cascade determined the available solution space and to generate synthesizable RTL for suitable co-processor architecture. No modifications were made to the original embedded software. Synopsys' Design Compiler® synthesis solution and the VCS® complete RTL verification solution were used to synthesize and validate the output from Cascade for delivery of the predicted gate count and performance figures for 0.13-micron technology.
"Synopsys has a long history of supporting emerging EDA companies who provide complementary parts of the design flow. Our customers expect us to enable a degree of validation of these new tools with respect to our trusted flows and we are happy to support this activity," stated Karen Bartleson, director of Interoperability, Synopsys, Inc
The benchmark project involved an open source embedded software implementation of a BCH error correction solution typically used in wireless applications. The end customer selected the example and set appropriate and meaningful goals in terms of gate count and performance. The source code was compiled, functionally verified and profiled on an ARM® processor using the ARM RealView® tool suite, and then imported into CriticalBlue's Cascade tool. Within Cascade, the profiling results were used to identify the appropriate software functions for offloading to a coprocessor, and the relevant target technology and system parameters were set up along with the gate count and performance constraints required by the customer. Cascade then automatically generated a series of candidate architectures to implement those software functions as a dedicated co-processor, and displayed them such that a customer software or hardware engineer could quickly and easily see how the co-processor candidates performed against the constraints. This is important in that the gate count and performance predictions be accurate compared with the results obtained later during hardware implementation.
Once the user identified the optimal co-processor architecture from the available candidates, Cascade generated synthesizable RTL code of the co-processor hardware, microcode to run on the co-processor and a testbench so that the user could verify that the functionality of the resulting co-processor was identical to that captured in the original embedded software and dataset.
"The purpose of validating the flow through the Synopsys RTL implementation flow was to verify the interoperability of the RTL code that Cascade generates and ensure the gate count and performance goal are met," commented David Stewart, CEO, CriticalBlue. "Our activity with Synopsys, gives end users the confidence that the design that Cascade generates seamlessly fits into the Synopsys verification and implementation flow, enabling our customers to shorten product development timelines."
About CriticalBlue
CriticalBlue is focused on delivering tools for accelerating software in embedded microprocessor applications to key design houses and semiconductor vendors in the telecommunication, automotive and multimedia sectors. The Cascade tool provides a broader range of implementation options within existing electronic design flows, as well as minimizing risk and development time. This is achieved by analyzing executable software code and automatically generating an appropriate hardware coprocessor, designed to accelerate tasks originally targeted at a general-purpose microprocessor. For more information, visit www.criticalblue.com.
Synopsys, Design Compiler and VCS are registered trademarks of Synopsys, Inc.
ARM is a registered trademark of ARM Limited. RealView is a trademark of ARM Limited. All other brands or product names are the property of their respective holders.
For more information, please contact:
David Stewart
CriticalBlue
+1 408 467 5091
Leslie Cumming
Skye Marketing Communications
+ 1 415 285 2352