Support

"The key to increasing the customer base for our silicon platforms is the creation of a level of abstraction that appeals to software engineers. CriticalBlue’s Cascade solution, which works directly from compiled embedded software with no coding or language restrictions, is the natural bridge which enables software applications to be rapidly deployed on Xilinx FPGA devices."

Software-Driven Design

Cascade synthesizes programmable coprocessors for implementation in a range of field-programmable logic arrays (FPGA) and system-on-FPGA families. CriticalBlue's product validations and customer evaluations are generally conducted and delivered on FPGA platforms, whether the final implementation is to be FPGA, SoC or Structured ASIC. Currently, Cascade supports the following device families:

Xilinx Virtex-II Platform FPGA
Xilinx Virtex-II Pro/Pro X FPGA
Xilinx Spartan-3/3E/3L FPGA
Xilinx Virtex-4 Multi-Platform FPGA

CriticalBlue is an active partner in Xilinx's ESL for FPGA Initiative. Xilinx is committed to continuously improving the ESL for FPGA flows by partnering with companies who provide innovative solutions for targeting C and other high level language based designs to FPGAs.

Microprocessor Support

Cascade synthesizes programmable coprocessors with two levels of support:

Level 1 is a fully automated front-to-back solution.
Level 2 is a fully automated hardware synthesis solution that requires some up-front executable software code translation by CriticalBlue. Level 2 support is upgraded to Level 1 in response to customer demand

Cascade currently supports the following microprocessors:

Any ARM CPU that uses the v4 or v5 instruction sets: Level 1 support.
PowerPC: Level 2 now; Level 1 support coming soon.
MicroBlaze: Level 2 support.

Cascade generates an optimized coprocessor in synthesizable RTL with synthesis scripts, an instruction- and bit-accurate C functional model, and a testbench that verifies the implementation with the same stimuli and expected responses as those of the CPU, ensuring functional equivalence. The implementation then proceeds through the designer's own system-on-chip (SoC), FPGA or structured ASIC design and verification flows.

Design Flow Support

Cascade's synthesizable RTL output has been fully tested and validated with Synopsys, Synplicity and Xilinx synthesis tools, and is fully integrated into the Xilinx ISE tool flow.

The verification approach has been validated with the Xilinx ISE tool flow and Mentor's ModelSim XE/PE. Cascade can target any Xilinx-populated board, without translation or modification. Consequently, no family-specific design kit is required.

Cascade also supports a MatLab-to-programmable-coprocessor design flow. The designer converts algorithms described in MatLab to C or C++ code, which can then be compiled for the CPU of choice. The designer then uses Cascade to synthesize a programmable coprocessor optimized to execute the algorithm.

Library Support

Cascade uses its own standard function blocks such as adders and shifters. Users can add new components to Cascade's library - either custom or vendor-specific blocks - and can explore the benefit of adding such blocks before making a deployment decision.

Custom function libraries can be incorporated into the Cascade-generated programmable coprocessor.
Vendor-specific library elements, e.g. memory blocks, are automatically used by Cascade when the user selects the vendor's technology type.

For a comprehensive overview of Cascades features and the problem that it solves, click here.

Partnerships