Freescale Platform Support Packages
The Freescale Platform Support Packages (PSPs) for Prism are designed to help developers targeting Freescale multicore processors including the QorIQ™, 8xxx, PowerQUICC®, POWER e200, StarCore DSP and i.MX 6 processor families.
The following support is available for Freescale devices
| PSP Name | Target Processors | Target OS | Threading API | PSP Levels | Available Models in Core PSP |
|---|---|---|---|---|---|
| POWER_e500 | POWER architecture devices based on the e500 core (QorIQ™, 8xxx, PowerQUICC®) | Linux | PThreads | Instruction, Core | POWER e500 |
| POWER-SIMICS | WindRiver Simics models of POWER architecture devices based on the e500 core (QorIQ™, 8xxx, PowerQUICC®) | Linux | PThreads | Instruction | N/A |
| POWER_e200 | POWER architecture devices based on the e200 core | Bare Metal | None | Instruction, Core | POWER e200 |
| i.MX 6 | ARMv7 architecture devices | Linux | PThreads | Instruction, Core | i.MX 6 |
| StarCore DSP | StarCore DSP devices | Bare Metal | None | Instruction, Core | StarCore Devices |
The Freescale POWER Instruction PSP supports the Power processor instruction set. The PSP is architecture specific, but not core or target system specific, allowing the use of a generic toolchain. The PSP is designed to enable quick application parallelization using what-if analysis, PThreads verification and tuning features.
- What-if analysis Demonstrates the impact of possible changes to your code or hardware. What if a function was made its own thread or if there was another core?
- PThreads Verification and Tuning Analysis of potential data races or dependencies. Iterative process of improvements
Together, these features provide the user with an insight into the benefits of running and optimizing multithreaded code on Freescale Power processors.
The Freescale i.MX 6 Core PSP is supports the i.MX 6 family of ARMv7 devices. In addition to core level features this provides:
- Enhanced code performance profiling. Provides per source line branch misprediction and interlock pipeline stall statistics.
- Cache Modelling and Analysis. Model and compare alternative cache architectures. Schedules can be generated showing performance impact on the application while the new Cache Performance view highlights source lines causing poor cache performance.
- Hardware Threading Analysis The balance of throughput from different hardware threads can be analyzed and shown